Memory Subsystem Performance Architect

Company: Qualcomm
Location: San Diego
Posted on: June 1, 2025

Job Description:

Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:The infrastructure IP Team consists of a multi-disciplinary group involved in the definition and design of Platform infrastructure HW components such as Memory controllers, System cache, System MMU and Interconnect that are implemented in all Qualcomm SoCs. This position primarily involves studying System Performance using cycle-accurate/approximate models and support both Infra IP level u-architecture optimizations as well as System level application performance verification. The ideal candidate should demonstrate the ability to understand the HW u-architecture of the Infrastructure components involved, in particular the memory system and interconnect, identify performance bottlenecks; define experiments and conduct data-driven performance analyses and debug using simulation; Ability to partner effectively with IP designers, Design Verification teams and System performance architects.Key Deliverables:

• Modeling and analysis of system cache, memory controller scheduling algorithms, and features
• Develop tests, test plans and testing infrastructure for new architecture/features
• Conduct in-depth analysis of product requirement dashboards, CPU and GPU benchmarks to identify memory bottlenecks and areas for improvement.
• Demonstrates good understanding of and conducts research on industry trends and innovations in memory subsystem to ensure solutions and deliverables align with best practices.
• Mentor young engineers and encourage good coding and performance analysis practices
• Drive model development best practices, coding guidelines and process automationsPreferred Qualifications:
  • Self-driven, methodical and process oriented.
  • Excellent oral and written communication
  • Sound understanding of System interconnect, Caches and Memory Technologies (e.g. LPDDR4/5)
  • Experience with SoC Performance analysis and debug in pre and/or Post-Silicon environments
  • Good understanding of QoS concepts
  • Good handle in Object oriented programming and general SW debug (C++)
  • Strong scripting skills (Perl/Python)
  • Experience with data analysis using Excel, R, Python etc.Minimum Qualifications:--- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.ORMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.ORPhD in Science, Engineering, or related field.Pay range and Other Compensation & Benefits:$115,600.00 - $173,400.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this .If you would like more information about this role, please contact .
    #J-18808-Ljbffr

Keywords: Qualcomm, Cerritos , Memory Subsystem Performance Architect, Professions , San Diego, California